More than 90% of the earth's crust is composed of Silica (SiO₂) or Silicate, making silicon the second most abundant element on earth. When sand glitters in sunlight, that's silica. Silicon is found in myriad compounds in nature and industry. Most importantly to technology, silicon is the principle platform for semiconductor devices. The most advanced semiconductor technologies of today and tomorrow require monocrystalline Silicon with precise uniform chemical characteristics, for instance controlled dopant and oxygen content. The process to transform raw silicon into a useable single-crystal substrate for modern semiconductor processes begins by mining for relatively pure Silicon Dioxide. Most silicon now is made by reduction of SiO₂ with Carbon in an electric furnace from 1500 to 2000^oC. With carefully selected pure sand, the result is commercial brown Metallurgical Grade Silicon of 97% purity or better. This is the silicon eventually used for semiconductors, but it must be further purified to bring impurities below the parts-per-billion level.

MG-Si is reacted with HCl to form trichlorosilane (TCS) in a fluidized-bed reactor (@300^oC) according to the chemical reaction Si + 3HCl --> SiHCl₃ + H₂. TCS is an intermediate compound for polysilicon manufacturing. In the course of converting MG-Si to TCS, impurities such as Fe, Al and B are removed. This ultra-pure TCS is subsequently vaporized (distilling the TCS achieves an even higher level of purity), diluted with H₂, and flowed into a deposition reactor where it is retransformed into elemental silicon. This polysilicon has typical contamination levels of less than .001 ppb.

Now that a high level of purity has been attained (99.999999999% eleven nines), the atomic structure of the silicon must be dealt with. A process known as Crystal Growing transforms polycrystalline silicon into samples with a singular crystal orientation, known as ingots. The Polysilicon is mechanically broken into 1 to 3 inch chunks and undergoes stringent surface etching and cleaning in a cleanroom environment. These chunks are then packed into quartz crucibles for meltdown (at 1420^oC) in a CZ furnace. A monocrystalline Silicon seed is installed into a seed shaft in the upper chamber of the furnace. Slowly, the seed is lowered so that it dips approximately 2mm into the Silicon melt. Next, the seed is slowly retracted from the surface allowing the melt to solidify at the boundary. As the seed pulls the Silicon from the melt, both the crucible and the seed are rotated in opposite directions to allow for an almost round crystal to form. CZ furnaces also must be very stable and isolated from vibrations. Once the proper crystal diameter is achieved, the seed lift is increased. This, along with the heat transfer from heater elements will control the diameter of the crystal. (Images from Wacker - How To Make Silicon)

During the growth process, the crucible slowly dissolves Oxygen into the melt that is incorporated into the final crystal in typical concentrations of around 25ppma. Intentional additions of dopants control the resistivity distribution of the final crystal. In addition to pull speed and heat transfer at the solid-liquid interface, heat dissipation during crystal cooling strongly determines microscopic defect characteristics in the final crystal. For modern CZ pulling systems, those variables can be accurately predicted by numerical simulations which allow designing the geometrical and thermal configuration of the CZ puller to the desired outcome of the crystals. Once the growth process is complete, the crystal is cooled inside the furnace for up to 7 hours. This gradual cooling allows the crystal lattice to stabilize and makes handling easier before transport to the next operation. For some applications, it is important to have even lower concentrations of impurity atoms (eg. Oxygen) than what can be achieved by CZ crystal growth. In this case, Float Zone Crystal Growth is used. In this process the end of a long polysilicon rod is locally melted and brought in contact with a monocrystalline Silicon seed. The melted zone slowly migrates through the poly rod leaving behind a final uniform crystal.

Ingots coming from crystal growing are slightly over-sized in diameter and typically not round. Hence, a machine employing a grindwheel shapes the ingot to the precision needed for wafer diameter control. Other grinding wheels are then used to carve a characteristic notch or a flat in order to define the proper orientation of the future wafer versus a particular crystallographic axis.

Wafer shaping involves a series of precise mechanical and chemical process steps that are necessary to turn the ingot segment into a functional wafer. It is during these steps that the wafer surfaces and dimensions are perfected to exacting detail. Each step is designed to bring the wafer into compliance with each customer specification. The first of these critical steps is Multi-Wiring Slicing. The dominant state of the art slicing technology is Multi-Wire Sawing (MWS). Here, a thin wire is arranged over cylindrical spools so that hundreds of parallel wire segments simultaneously travel through the ingot. While the saw as a whole slowly moves through the ingot, the individual wire segments conduct a translational motion always bringing fresh wire into contact with the Silicon. The sawing effect is actually achieved by SiC or other grinding agents that run along the rotating wire. After MWS the wafers are cleaned and consolidated into process lots and transported to the next operation. The sideward deflection of the wire saw can lead to marks or "waviness" on the wafer surface and wire-to-wire thickness variations cause wafer thickness variations of up to several microns. Wafers are thus exposed to a complex polishing process.

State of the art front surface polishing is performed generally in a two step process. One mechanical polishing step (lapping) to create flatness followed by a chemical etch to create smoothness. After polishing, the wafers are subjected to a final clean.  Lapping the wafers removes saw marks and surface defects from the front and backside of the wafers, thins the wafer to spec and relieves much of the stress accumulated in the wafer during the sawing process. Edge rounding is normally done before or after lapping and is very important to the structural integrity of the wafer. The edges of 200mm and 300mm wafers are rounded even in the notch area. On the best prime wafers the edges themselves are also highly polished, a step that can improve cleaning results on wafers and reduce breakage up to 400%. Process Specialties has seen a notable yield differential between poorly and perfectly edge rounded material.

For many applications, the quality of a polished wafer is not sufficient. This is mainly due to defects generated during crystal growth in the bulk of the wafer. These defects, when they are within a few microns to the surface, can deteriorate the performance of devices built on top. Presently, the best solution to this problem is to deposit an additional layer of high purity Silicon on the top of a polished wafer substrate (an Epi Layer).

After a final clean and polish, wafers are ready for a final inspection before delivery.


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